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This post is part of a series – click here for the index. In our previous post, I gave a brief introduction on how to create simple combinatorial hardware in Clash and we ended up with a partly working, ugly circular stack implementation. In this post we will fix the bug, tidy up the code…
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I work a lot with FPGAs, and I have been interested in any language that makes it easier to develop hardware for them. Since I am currently a PhD student at the CAES group of the Unversity of Twente, I have been interested in learning Clash or CAES Language for Synthesizable Hardware, a functional hardware description language built…
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This post is part of a series – click here for the index. For FPGA development, VHDL was my default language for a while. That started to shift towards Verilog when I discovered Yosys-SMTBMC created by Clifford Wolf, which is a formal verification tool for hardware. However, recently I’ve been exploring other HDL languages and…
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